Artificial Intelligence (AI) is booming and so does also its energy footprint. The exponentially increasing scale of Deep Learning (DL) models comes at the cost of high computational power and energy requirements, with the daily power consumed by highly acclaimed Large Language Models (LLMs) like ChatGPT-3 being already at 0.5 GWh. With current projections forecasting that the computational power requirements will double every 5-6 months, meeting the compute power requirements of next-generation AI applications without yielding an energy boom, necessitates nothing less than a “tectonic shift” in the underlying computing hardware.
In this challenging landscape, despite the initial optimism regarding photonic-based computing as a high-speed and low-power alternative, photonic neuromorphic circuitry is still struggling to reach its theoretical projected energy efficiency of 10s of fJ/MAC and operating speeds of 50 GHz. Meeting these ambitious goals, necessitates innovations across the whole photonic value chain and integration technologies, along with a holistic design approach capable of aligning the photonic building blocks along an optimal architectural framework and Deep Learning Models.
Gathered around this idea, 5 partners across the European Union and Republic of Korea have united in launching the HAETAE project, aiming to develop a novel photonic computing platform that can optimize speed, energy and size-efficiency across all its constituent circuitry by utilizing and advancing the best-in-class technology and material platforms. Specifically, HAETAE – “Heterogeneously Integrated Multi‐material Photonic Chiplets for Neuromorphic Photonic Transfer Learning AI Engines” – is a new 3-year long HORIZON-JU-Chips / Nation Research Foundation of Korea (Republic of Korea) project, launched on October 1st, 2024, aiming to release a whole new class of energy efficient Transfer Learning -enhanced photonic accelerators with up to 50 Gbaud operating frequencies and 15x better energy efficiency, comparing to current state-of-the art.
Following a holistic hardware/software co-design approach, HAETAE targets the following objectives:
i) Develop a converged InP/Si3N4/SOI multi-material platform, enabled by novel heterogeneous integration approaches such as micro transfer printing (uTP)
ii) Elevate photonic MEMs device architectures to non-volatile implementations, for low-loss and zero-power photonic Matrix Multiplication engines
iii) Blend both platforms into a powerful unified photonic multi-chiplet accelerator via novel chiplet bonding approaches
iv) Align photonic neural network accelerator design with the latest innovations in AI, by developing a new-class of Transfer Learning enabled photonic systems-on-chip
v) Pave the way for wide industry adoption, by experimentally validating its technologies across the DC communication sector, cybersecurity and Transformer-based Neural Network applications
HAETAE’s consortium is strategically assembled to include the entire technology development chain, comprising a high-quality blend of industrial and academic partners which will work complementary towards satisfying all possible technological requirements and exploitation paths. HAETAE’s team has been built for success, uniting expertise from across the Republic of Korea and the European Union: a) Three leading universities (AUTH, KAIST, DGIST)-bring pioneering advancements in neuromorphic photonics to HAETAE, covering all critical integration platforms: KAIST and DGIST specializing in MEMS-based photonic neural networks (PNNs), and AUTH in silicon-based PNNs b) A renowned R&D centre (IMEC) with a track-record on developing cutting-edge Silicon Photonic technology, and finally c) An established SME (AKHETONICS) with strong R&D in the fields of all-optical non-linearities and computing. The synergy between all partners ensures that the development work always remains along the right direction: system design, modelling, testing and evaluation on the basis of valid market application scenarios are indispensable activities to enable HAETAE to maximize its exploitation potential, providing a credible path for breeding innovation into tangible outcomes.
The kick-off meeting of the HAETAE project took place online on November 4th, 2024, marking the official start of this ambitious initiative. During the meeting, the objectives of HAETAE were thoroughly discussed and participants reviewed the key milestones, set clear targets for each phase, and outlined collaborative efforts to accelerate innovation in HAETAE photonic accelerator architectures. The meeting fostered a strong foundation for the consortium to drive progress towards achieving HAETAE groundbreaking goals in photonic computing.
The outcome of the HAETAE project – a radically new photonic accelerator technology - perfectly responds to the pressing industrial needs for high-speed, low-cost, energy- and size-efficient neuromorphic chips, offering a unique chance to strengthen the competitiveness of the photonic industries in the European Union and Republic of Korea, while also creating valuable collaboration between the two participating entities.
Grant Agreement: 101194393
Programme: Horizon-JU-Chips-2024-3-RIA
Duration: 01/10/2024 – 31/09/2027 (36 Months)
Budget
Overall Cost: 2,899,956.00 €
EU Contribution: € 1,499,956.00 €
Coordinator: Aristotle University of Thessaloniki, GR
